Design of Full Adder Using Subthreshold DTPT Logic

Abstract

As technology scaling has enabled small, design of digital circuits optimal for subthreshold region is becoming an active area for ultra low power applications. This paper presents the design of full adder using Subthreshold Dynamic Threshold Pass Transistor (Sub-DTPT) logic to achieve low power with acceptable performance. The simulations are carried out in cadence 90nm technology for V_dd=0.2V and 1.2V. From the simulations the Power Delay Product (PDP) of the proposed design is found to be extremely low in subthreshold region and is reduced by more than 80% when compared with the earlier reports. In strong inversion region the proposed adder is achieved more than 50% savings in delay when compared with the existing designs.