Review of recent trends in Coarse Grain Reconfigurable Architectures for signal processing applications

Abstract

 Coarse grained reconfigurable architecture got the attention of researchers working in designing computing architectures for processing massive streaming data associated with the multimedia applications in portable entertainment and communication electronics. The algorithms for processing audio, video, and graphics are very complex in nature. These data intensive computation algorithms belong to the domain of signal processing. As the complexity of algorithms increases, a matching improvement in speed performance of the hardware becomes essential to maintain the quality of service. The observed growth of algorithmic complexity is much higher than the growth rate of integration density governed by Moore’s law. Also, the constraints on memory bandwidth in the traditional von Neumann architectures along with the slow growth in the battery capacity demands a paradigm shift in computer architecture design. Reconfigurable hardware architecture is proposed as a possible alternative in this regard. The reconfigurable architectures are designed to exploit the regular and repetitive structure of signal processing algorithms and the coarse grained processing elements are designed to match with the word level granularity of these complex algorithms. The research shows that the coarse grain reconfigurable architectures with heterogeneous processing elements are a better option for system design in DSP applications which exploit granularity matching between the algorithms and the processing hardware, and also the inherent parallelism of DSP algorithms for the realization of low power DSP systems.