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Power dissipation is one of the on-demand problems of low power Very large-scale integration (VLSI) circuit design and it is related with threshold voltage. Generally, the subthreshold leakage current and the leakage power dissipation are increased while reducing the threshold voltage. The overall performance of the total power dissipation is completely depending on this leakage power dissipation. This leakage power causes the components that are functioned by battery for a long period washed-out rapidly. In this paper, a new read decoupled and write enhanced macro memory design is proposed using transistor stacking and reversible logic to reduce the leakage power. For the reduction of power consumption of Static Random Access Memory (SRAM) that are placed in System on Chips (SoCs), the proposed model includes three features: a reversible cross coupled stacked inverter with Transmission gate is adopted in SRAM cell to reduce the leakage power, a reversible differential power generator is adopted to improve the write ability of the design with less power and a read burst mode is used to reduce the read energy while reading consecutive addresses. Furthermore, a reversible logic is applied in all the peripheral circuits, which gives additional level of confidence in terms of leakage power. The simulation results show that the leakage power of the proposed macro memory design is reduced to 2.22nW at 0.6V supply, which is 4.32nW less than that of the conventional macro design. Furthermore, the write and read power consumption of the proposed macro design is reduced by 57% and 66% as compared to conventional one at a supply voltage of 0.6 V.