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Rani MU, N. SSR, B. RN. Leakage Power Reduction in Read and Write Enhanced Macro Memory Circuit Design Using Transistor Stacking and Reversible Approach. ASSA [Internet]. 20Apr.2022 [cited 3Jul.2022];22(1):130-47. Available from: https://ijassa.ipu.ru/index.php/ijassa/article/view/1177