RANI, Mucherla Usha; N., Siva Sankar Reddy; B., Rajendra Naik. Leakage Power Reduction in Read and Write Enhanced Macro Memory Circuit Design Using Transistor Stacking and Reversible Approach. Advances in Systems Science and Applications, [S. l.], v. 22, n. 1, p. 130–147, 2022. DOI: 10.25728/assa.2022.22.1.1177. Disponível em: https://ijassa.ipu.ru/index.php/ijassa/article/view/1177. Acesso em: 25 nov. 2024.